Flash memory with low tunnel barrier interpoly insulators

ABSTRACT

Structures and methods for Flash memory with low tunnel barrier intergate insulators are provided. The non-volatile memory includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator. The low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of PbO, Al 2 O 3 , Ta 2 O 5 , TiO 2 , ZrO 2 , and Nb 2 O 5 . The floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator. And, the control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. Application No. 10/931,704filed Sep. 1, 2004, which is a divisional of U.S. Application No.09/945,507 filed Aug. 30, 2001, now issued as U.S. Pat. No. 7,068,544,both of which are incorporated herein by reference.

This application is related to the following co-pending, commonlyassigned U.S. patent applications: “DRAM Cells with Repressed MemoryMetal Oxide Tunnel Insulators,” Ser. No. 09/945,395, “Programmable ArrayLogic or Memory Devices with Asymmetrical Tunnel Barriers,” Ser. No.09/943,134, “Dynamic Electrically Alterable Programmable Memory withInsulating Metal Oxide Interpoly Insulators,” Ser. No. 09/945,498, and“Field Programmable Logic Arrays with Metal Oxide and/or Low TunnelBarrier Interpoly Insulators,” Ser. No. 09/945,512, “SRAM Cells withRepressed Floating Gate Memory, Metal Oxide Tunnel InterpolyInsulators,” Ser. No. 09/945,554, “Programmable Memory Address andDecode Devices with Low Tunnel Barrier Interpoly Insulators,” Ser. No.09/945,500, which are filed on even date herewith and each of whichdisclosure is herein incorporated by reference.

FIELD OF THE INVENTION

The present invention relates generally to integrated circuits, and inparticular to Flash memory with low tunnel barrier interpoly insulators.

BACKGROUND OF THE INVENTION

Flash memories have become widely accepted in a variety of applicationsranging from personal computers, to digital cameras and wireless phones.Both INTEL and AMD have separately each produced about one billionintegrated circuit chips in this technology.

The original EEPROM or EARPROM and flash memory devices described byToshiba in 1984 used the interpoly dielectric insulator for erase. (Seegenerally, F. Masuoka et al., “A new flash EEPROM cell using triplepolysilicon technology,” IEEE Int. Electron Devices Meeting, SanFrancisco, pp. 464-67, 1984; F. Masuoka et al., “256K flash EEPROM usingtriple polysilicon technology,” IEEE Solid-State Circuits Conf.,Philadelphia, pp. 168-169, 1985). Various combinations of silicon oxideand silicon nitride were tried. (See generally, S. Mori et al.,“reliable CVD inter-poly dialectics for advanced E&EEPROM,” Symp. OnVLSI Technology, Kobe, Japan, pp. 16-17, 1985). However, the rough topsurface of the polysilicon floating gate resulted in, poor qualityinterpoly oxides, sharp points, localized high electric fields,premature breakdown and reliability problems.

Widespread use of flash memories did not occur until the introduction ofthe ETOX cell by INTEL in 1988. (See generally, U.S. Pat. No. 4,780,424,“Process for fabricating electrically alterable floating gate memorydevices,” 25 Oct. 1988; B. Dipert and L. Hebert, “Flash memory goesmainstream,” IEEE Spectrum, pp. 48-51, October, 1993; R. D. Pashley andS. K. Lai, “Flash memories, the best of two worlds,” IEEE Spectrum, pp.30-33, December 1989). This extremely simple cell and device structureresulted in high densities, high yield in production and low cost. Thisenabled the widespread use and application of flash memories anywhere anon-volatile memory function is required. However, in order to enable areasonable write speed the ETOX cell uses channel hot electroninjection, the erase operation which can be slower is achieved byFowler-Nordhiem tunneling from the floating gate to the source. Thelarge barriers to electron tunneling or hot electron injection presentedby the silicon oxide-silicon interface, 3.2 eV, result in slow write anderase speeds even at very high electric fields. The combination of veryhigh electric fields and damage by hot electron collisions in the oxideresult in a number of operational problems like soft erase error,reliability problems of premature oxide breakdown and a limited numberof cycles of write and erase.

Other approaches to resolve the above described problems include; theuse of different floating gate materials, e.g. SiC, SiOC, GaN, andGaAIN, which exhibit a lower work function (see FIG. 1A), the use ofstructured surfaces which increase the localized electric fields (seeFIG. 1B), and amorphous SiC gate insulators with larger electronaffinity, χ, to increase the tunneling probability and reduce erase time(see FIG. 1C).

One example of the use of different floating gate (FIG. 1A) materials isprovided in U.S. Pat. No. 5,801,401 by L. Forbes, entitled “FLASH MEMORYWITH MICROCRYSTALLINE SILICON CARBIDE AS THE FLOATING GATE STRUCTURE.”Another example is provided in U.S. Pat. No. 5,852,306 by L. Forbes,entitled “FLASH MEMORY WITH NANOCRYSTALLINE SILICON FILM AS THE FLOATINGGATE.” Still further examples of this approach are provided in pendingapplications by L. Forbes and K. Ahn, entitled “DYNAMIC RANDOM ACCESSMEMORY OPERATION OF A FLASH MEMORY DEVICE WITH CHARGE STORAGE ON A LOWELECTRON AFFINITY GaN OR GaAIN FLOATING GATE,” Ser. No. 08/908,098, and“VARIABLE ELECTRON AFFINITY DIAMOND-LIKE COMPOUNDS FOR GATES IN SILICONCMOS MEMORIES AND IMAGING DEVICES,” Ser. No. 08/903,452.

An example of the use of the structured surface approach (FIG. 1B) isprovided in U.S. Pat. No. 5,981,350 by J. Geusic, L. Forbes, and K. Y.Ahn, entitled “DRAM CELLS WITH A STRUCTURE SURFACE USING A SELFSTRUCTURED MASK.” Another example is provided in U.S. Pat. No. 6,025,627by L. Forbes and J. Geusic, entitled “ATOMIC LAYER EXPITAXY GATEINSULATORS AND TEXTURED SURFACES FOR LOW VOLTAGE FLASH MEMORIES.”

Finally, an example of the use of amorphous SiC gate insulators (FIG.1C) is provided in U.S. patent application Ser. No. 08/903,453 by L.Forbes and K. Ahn, entitled “GATE INSULATOR FOR SILICON INTEGRATEDCIRCUIT TECHNOLOGY BY THE CARBURIZATION OF SILICON.”

Additionally, graded composition insulators to increase the tunnelingprobability and reduce erase time have been described by the sameinventors. (See, L. Forbes and J. M. Eldridge, “GRADED COMPOSITION GATEINSULATORS TO REDUCE TUNNELING BARRIERS IN FLASH MEMORY DEVICES,”application Ser. No. 09/945,514.

However, all of these approaches relate to increasing tunneling betweenthe floating gate and the substrate such as is employed in aconventional ETOX device and do not involve tunneling between thecontrol gate and floating gate through and inter-poly dielectric.

Therefore, there is a need in the art to provide improved flash memorydensities while avoiding the large barriers to electron tunneling or hotelectron injection presented by the silicon oxide-silicon interface, 3.2eV, which result in slow write and erase speeds even at very highelectric fields. There is also a need to avoid the combination of veryhigh electric fields and damage by hot electron collisions in the whichoxide result in a number of operational problems like soft erase error,reliability problems of premature oxide breakdown and a limited numberof cycles of write and erase. Further, when using an interpolydielectric insulator erase approach, the above mentioned problems ofhaving a rough top surface on the polysilicon floating gate whichresults in, poor quality interpoly oxides, sharp points, localized highelectric fields, premature breakdown and reliability problems must beavoided.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1C illustrate a number of previous methods for reducingtunneling barriers in Flash memory.

FIG. 2 illustrates one embodiment of a floating gate transistor, ornon-volatile memory cell, according to the teachings of the presentinvention.

FIG. 3 illustrates another embodiment of a floating gate transistor, ornon-volatile memory cell, according to the teachings of the presentinvention.

FIG. 4 is a perspective view illustrating an array of silicon pillarsformed on a substrate as used in one embodiment according to theteachings of the present invention.

FIGS. 5A-5E are cross sectional views taken along cut line 5-5 from FIG.4 illustrating a number of floating gate and control gate configurationswhich are included in the scope of the present invention.

FIGS. 6A-6D illustrate a number of address coincidence schemes can beused together with the present invention.

FIG. 7A is an energy band diagram illustrating the band structure atvacuum level with the low tunnel barrier interpoly insulator accordingto the teachings of the present invention.

FIG. 7B is an energy band diagram illustrating the band structure duringan erase operation of electrons from the floating gate to the controlgate across the low tunnel barrier interpoly insulator according to theteachings of the present invention.

FIG. 7C is a graph plotting tunneling currents versus the appliedelectric fields (reciprocal applied electric field shown) for a numberof barrier heights.

FIG. 8 illustrates a block diagram of an embodiment of an electronicsystem 801 according to the teachings of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following detailed description of the invention, reference ismade to the accompanying drawings which form a part hereof, and in whichis shown, by way of illustration, specific embodiments in which theinvention may be practiced. The embodiments are intended to describeaspects of the invention in sufficient detail to enable those skilled inthe art to practice the invention. Other embodiments may be utilized andchanges may be made without departing from the scope of the presentinvention. In the following description, the terms wafer and substrateare interchangeably used to refer generally to any structure on whichintegrated circuits are formed, and also to such structures duringvarious stages of integrated circuit fabrication. Both terms includedoped and undoped semiconductors, epitaxial layers of a semiconductor ona supporting semiconductor or insulating material, combinations of suchlayers, as well as other such structures that are known in the art.

The term “horizontal” as used in this application is defined as a planeparallel to the conventional plane or surface of a wafer or substrate,regardless of the orientation of the wafer or substrate. The term“vertical” refers to a direction perpendicular to the horizontal asdefined above. Prepositions, such as “on”, “side” (as in “sidewall”),“higher”, “lower”, “over” and “under” are defined with respect to theconventional plane or surface being on the top surface of the wafer orsubstrate, regardless of the orientation of the wafer or substrate. Thefollowing detailed description is, therefore, not to be taken in alimiting sense, and the scope of the present invention is defined onlyby the appended claims, along with the full scope of equivalents towhich such claims are entitled.

The present invention, describes the use of metal oxide inter-polydielectric insulators between the control gate and the floating gate. Anexample is shown in FIG. 2 for a planar structure, or horizontalnon-volatile memory cell. According to the teachings of the presentinvention. The use of metal oxide films for this purpose offer a numberof advantages including:

(i) Flexibility in selecting a range of smooth metal film surfaces andcompositions that can be oxidized to form tunnel barrier insulators.

(ii) Employing simple “low temperature oxidation” to produce oxide filmsof highly controlled thickness, composition, purity and uniformity.(iii) Avoiding inadvertent inter-diffusion of the metal and silicon aswell as silicide formation since the oxidation can be carried out atsuch low temperatures.

(iv) Using metal oxides that provide desirably lower tunnel barriers,relative to barriers currently used such as SiO₂.

(v) Providing a wide range of higher dielectric constant oxide filmswith improved capacitance characteristics.

(vi) Providing a unique ability to precisely tailor tunnel oxide barrierproperties for various device designs and applications.

(vii) Permitting the use of thicker tunnel barriers, if needed, toenhance device performance and its control along with yield andreliability.

(viii) Developing layered oxide tunnel barriers by oxidizing layeredmetal film compositions in order, for example, to enhance device yieldsand reliability more typical of single insulating layers.

(ix) Eliminating soft erase errors caused by the current technique oftunnel erase from floating gate to the source.

FIG. 2 illustrates one embodiment of a floating gate transistor, ornon-volatile memory cell 200, according to the teachings of the presentinvention. As shown in FIG. 2, the non-volatile memory cell 200 includesa first source/drain region 201 and a second source/drain region 203separated by a channel region 205 in a substrate 206. A floating gate209 opposes the channel region 205 and is separated therefrom by a gateoxide 211. A control gate 213 opposes the floating gate 209. Accordingto the teachings of the present invention, the control gate 213 isseparated from the floating gate 209 by a low tunnel barrier intergateinsulator 215.

In one embodiment of the present invention, low tunnel barrier intergateinsulator 215 includes a metal oxide insulator selected from the groupconsisting of lead oxide (PbO) and aluminum oxide (A₂O₃). In analternative embodiment of the present invention, the low tunnel barrierintergate insulator 215 includes a transition metal oxide and thetransition metal oxide is selected from the group consisting of Ta₂O₅,TiO₂, ZrO₂, and Nb₂O₅. In still another alternative embodiment of thepresent invention, the low tunnel barrier intergate insulator 215includes a Perovskite oxide tunnel barrier.

According to the teachings of the present invention, the floating gate209 includes a polysilicon floating gate 209 having a metal layer 216formed thereon in contact with the low tunnel barrier intergateinsulator 215. Likewise, the control gate 213 includes a polysiliconcontrol gate 213 having a metal layer 217 formed thereon in contact withthe low tunnel barrier intergate insulator 215. In this invention, themetal layers, 216 and 217, are formed of the same metal material used toform the metal oxide interpoly insulator 215.

FIG. 3 illustrates another embodiment of a floating gate transistor, ornon-volatile memory cell 300, according to the teachings of the presentinvention. As shown in the embodiment of FIG. 3, the non-volatile memorycell 300 includes a vertical non volatile memory cell 300. In thisembodiment, the non-volatile memory cell 300 has a first source/drainregion 301 formed on a substrate 306. A body region 307 including achannel region 305 is formed on the first source/drain region 301. Asecond source/drain region 303 is formed on the body region 307. Methodsfor forming such a vertical transistor structure are disclosed in U.S.Pat. No. 6,135,175, entitled “Memory Address Decode Array with verticaltransistors, which is incorporated herein by reference. A floating gate309 opposes the channel region 305 and is separated therefrom by a gateoxide 311. A control gate 313 opposes the floating gate 309. Accordingto the teachings of the present invention, the control gate 313 isseparated from the floating gate 309 by a low tunnel barrier intergateinsulator 315.

According to the teachings of the present invention, the low tunnelbarrier intergate insulator 315 includes a metal oxide insulator 315selected from the group consisting of PbO, Al₂O₃, Ta₂O₅, TiO₂, ZrO₂,Nb₂O₅. In still another alternative embodiment of the present invention,the low tunnel barrier intergate insulator 315 includes a Perovskiteoxide tunnel barrier. The floating gate 309 includes a polysiliconfloating gate 309 having a metal layer 316 formed thereon in contactwith the low tunnel barrier intergate insulator 315. The control gate313 includes a polysilicon control gate 313 having a metal layer 317formed thereon in contact with the low tunnel barrier intergateinsulator 315.

As shown in FIG. 3, the floating gate 309 includes a vertical floatinggate 309 formed alongside of the body region 307. In the embodimentshown in FIG. 3, the control gate 313 includes a vertical control gate313 formed alongside of the vertical floating gate 309.

As will be explained in more detail below, the floating gate 309 andcontrol gate 313 orientation shown in FIG. 3 is just one embodiment fora vertical non volatile memory cell 300, according to the teachings ofthe present invention. In other embodiments, explained below, thefloating gate includes a horizontally oriented floating gate formedalongside of the body region. In this alternative embodiment, thecontrol gate includes a horizontally oriented control gate formed abovethe horizontally oriented floating gate.

FIG. 4 is a perspective view illustrating an array of silicon pillars400-1, 400-2, 400-3, . . . , 400-N, formed on a substrate 406 as used inone embodiment according to the teachings of the present invention. Aswill be understood by one of ordinary skill in the art upon reading thisdisclosure, the substrates can be (i) conventional p-type bulk siliconor p-type epitaxial layers on p+ wafers, (ii) silicon on insulatorformed by conventional SIMOX, wafer bonding and etch back or silicon onsapphire, or (iii) small islands of silicon on insulator utilizingtechniques such as described in more detail in U.S. Pat. No. 5,691,230,by Leonard Forbes, entitled “Technique for Producing Small Islands ofSilicon on Insulator,” issued Nov. 25, 1997, which is incorporatedherein by reference.

As shown in FIG. 4, each pillar in the array of silicon pillars 400-1,400-2, 400-3, . . . , 400-N, includes a first source/drain region 401and a second source/drain region 403. The first and the secondsource/drain regions, 401 and 403, are separated by a body region 407including channel regions 405. As shown in FIG. 4, a number of trenches430 separate adjacent pillars in the array of silicon pillars 400-1,400-2, 400-3, . . . , 400-N. Trenches 430 are referenced in connectionwith the discussion which follows in connection with FIGS. 5A-5E.

FIGS. 5A-5E are cross sectional views taken along cut line 5-5 from FIG.4. As mentioned above in connection with FIG. 3, a number of floatinggate and control gate configurations are included in the presentinvention. FIG. 5A illustrates one such embodiment of the presentinvention. FIG. 5A illustrates a first source/drain region 501 andsecond source/drain region 503 for a non-volatile memory cell 500 formedaccording to the teachings of the present invention. As shown in FIG. 5,the first and second source/drain regions, 501 and 503, are contained ina pillar of semiconductor material, and separated by a body region 507including channel regions 505. As shown in the embodiments of FIGS.5A-5E, the first source/drain region 501 is integrally connected to aburied sourceline 525. As one or ordinary skill in the art willunderstand upon reading this disclosure the buried sourceline 525 is beformed of semiconductor material which has the same doping type as thefirst source/drain region 501. In one embodiment, the sourceline 525 isformed of semiconductor material of the same doping as the firstsource/drain region 501, but is more heavily doped than the firstsource/drain region 501.

As shown in the embodiment of FIG. 5A, a pair of floating gates 509-1and 509-2 are formed in each trench 530 between adjacent pillars whichform memory cells 500-1 and 500-2. Each one of the pair of floatinggates, 509-1 and 509-2, respectively opposes the body regions 507-1 and507-2 in adjacent pillars 500-1 and 500-2 on opposing sides of thetrench 530.

In this embodiment, a single control gate 513 is shared by the pair offloating gates 509-1 and 509-2 on opposing sides of the trench 530. Asone of ordinary skill in the art will understand upon reading thisdisclosure, the shared single control gate 513 can include an integrallyformed control gate line. As shown in FIG. 5A, such an integrally formedcontrol gate line 513 can be one of a plurality of control gate lineswhich are each independently formed in the trench, such as trench 530,below the top surface of the pillars 500-1 and 500-2 and between thepair of floating gates 509-1 and 509-2. In one embodiment, according tothe teachings of the present invention, each floating gate, e.g. 509-1and 509-2, includes a vertically oriented floating gate having avertical length of less than 100 nanometers.

As shown in the embodiment of FIG. 5B, a pair of floating gates 509-1and 509-2 are formed in each trench 530 between adjacent pillars whichform memory cells 500-1 and 500-2. Each one of the pair of floatinggates, 509-1 and 509-2, respectively opposes the body regions 507-1 and507-2 in adjacent pillars 500-1 and 500-2 on opposing sides of thetrench 530.

In the embodiment of FIG. 5B, a plurality of control gate lines areagain formed in trenches, e.g. trench 530, below the top surface of thepillars, 500-1 and 500-2, and between the pair of floating gates 509-1and 509-2. However, in this embodiment, each trench, e.g. 530, houses apair of control gate lines, shown as 513-1 and 513-2. Each one of thepair of control gate lines 513-1 and 513-2 addresses the floating gates,509-1 and 509-2 respectively, on opposing sides of the trench 530. Inthis embodiment, the pair of control gate lines, or control gates 513-1and 513-2 are separated by an insulator layer.

As shown in the embodiment of FIG. 5C, a pair of floating gates 509-1and 509-2 are again formed in each trench 530 between adjacent pillarswhich form memory cells 500-1 and 500-2. Each one of the pair offloating gates, 509-1 and 509-2, respectively opposes the body regions507-1 and 507-2 in adjacent pillars 500-1 and 500-2 on opposing sides ofthe trench 530.

In the embodiment of FIG. 5C, the plurality of control gate lines aredisposed vertically above the floating gates. That is, in oneembodiment, the control gate lines are located above the pair offloating gates 509-1 and 509-2 and not fully beneath the top surface ofthe pillars 500-1 and 500-2. In the embodiment of FIG. 5C, each pair offloating gates, e.g. 509-1 and 509-2, in a given trench shares a singlecontrol gate line, or control gate 513.

As shown in the embodiment of FIG. 5D, a pair of floating gates 509-1and 509-2 are formed in each trench 530 between adjacent pillars whichform memory cells 500-1 and 500-2. Each one of the pair of floatinggates, 509-1 and 509-2, respectively opposes the body regions 507-1 and507-2 in adjacent pillars 500-1 and 500-2 on opposing sides of thetrench 530.

In the embodiment of FIG. 5D, the plurality of control gate lines aredisposed vertically above the floating gates. That is, in oneembodiment, the control gate lines are located above the pair offloating gates 509-1 and 509-2 and not fully beneath the top surface ofthe pillars 500-1 and 500-2. However, in the embodiment of FIG. 5D, eachone of the pair of floating gates, e.g. 509-1 and 509-2, is addressed byan independent one of the plurality of control lines or control gates,shown in FIG. 5D as 513-1 and 513-2.

As shown in the embodiment of FIG. 5E, a single floating gate 509 isformed in each trench 530 between adjacent pillars which form memorycells 500-1 and 500-2. According to the teachings of the presentinvention, the single floating gate 509 can be either a verticallyoriented floating gate 509 or a horizontally oriented floating gate 509formed by conventional processing techniques, or can be a horizontallyoriented floating gate 509 formed by a replacement gate technique suchas described in a copending application, entitled “Flash Memory withUltrathin Vertical Body Transistors,” by Leonard Forbes and Kie Y. Ahn,application Ser. No. 09/780,169. In one embodiment of the presentinvention, the floating gate 509 has a vertical length facing the bodyregion 505 of less than 100 nm. In another embodiment, the floating gate509 has a vertical length facing the body region 505 of less than 50 nm.In one embodiment, as shown in FIG. 5E, the floating gate 509 is shared,respectively, with the body regions 507-1 and 507-2, including channelregions 505-1 and 505-2, in adjacent pillars 500-1 and 500-2 located onopposing sides of the trench 530.

As one of ordinary skill in the art will understand upon reading thisdisclosure, in each of the embodiments described above in connectionwith FIGS. 5A-5E the floating gates 509 are separated from the controlgate lines, or control gates 513 with a low tunnel barrier intergateinsulator in accordance with the descriptions given above in connectionwith FIG. 3. The modifications here are to use tunneling through theinterpoly dielectric to realize flash memory devices. The verticaldevices include an extra flexibility in that the capacitors, e.g. gateoxide and intergate insulator, are easily fabricated with differentareas. This readily allows the use of very high dielectric constantinter-poly dielectric insulators with lower tunneling barriers.

FIGS. 6A-6D illustrate that a number of address coincidence schemes canbe used together with the present invention. FIG. 6A illustrates a NORflash memory array 610 having a number of non-volatile memory cells600-1, 600-2, 600-3, using a coincidence address array scheme. Forpurposes of illustration, FIG. 6A shows a sourceline 625 coupled to afirst source/drain region 601 in each of the number of non-volatilememory cells 600-1, 600-2, 600-3. The sourceline is shown oriented in afirst selected direction in the flash memory array 610. In FIG. 6A, anumber of control gate lines 630 are shown oriented in a second selecteddirection in the flash memory array 610. As shown in FIG. 6A, the numberof control gate lines 630 are coupled to, or integrally formed with thecontrol gates 613 for the number of non-volatile memory cells 600-1,600-2, 600-3. As shown in FIG. 6A, the second selected direction isorthogonal to the first selected direction. Finally, FIG. 6A shows anumber of bitlines 635 oriented in a third selected direction in theflash memory array 610. As shown in FIG. 6A, the number of bitlines arecoupled to the second source/drain regions in the number of non-volatilememory cells 600-1, 600-2, 600-3. In the embodiment shown in FIG. 6A thethird selected direction is parallel to the second selected directionand the number of control gate lines 630 serve as address lines. Also,as shown in FIG. 6A, the flash memory array 610 includes a number ofbackgate or substrate/well bias address lines 640 coupled to thesubstrate.

Using FIG. 6A as a reference point, FIGS. 6B-6D illustrate of top viewfor three different coincidence address scheme layouts suitable for usewith the present invention. First, FIG. 6B provides the top view layoutof the coincidence address scheme described in connection with FIG. 6A.That is, FIG. 6B illustrates a number of sourcelines 625 oriented in afirst selected direction, a number of control gate lines 630 oriented ina second selected direction, and a number of bitlines 635 oriented in athird selected direction for the flash memory array 600. As explainedabove in connection with FIG. 6A, in this embodiment, the second andthird selected direction are parallel to one another and orthogonal tothe first selected direction such that the number of control gate lines630 serve as address lines.

FIG. 6C provides the top view layout of another coincidence addressscheme according to the teachings of the present invention. This is,FIG. 6C illustrates a number of sourcelines 625 oriented in a firstselected direction, a number of control gate lines 630 oriented in asecond selected direction, and a number of bitlines 635 oriented in athird selected direction for the flash memory array 600. In theembodiment of FIG. 6C, the first selected direction and the thirdselected direction are parallel to one another and orthogonal to thesecond selected direction. In this embodiment, the number of controlgate lines 630 again serve as address lines.

FIG. 6D provides the top view layout of yet another coincidence addressscheme according to the teachings of the present invention. This is,FIG. 6D illustrates a number of sourcelines 625 oriented in a firstselected direction, a number of control gate lines 630 oriented in asecond selected direction, and a number of bitlines 635 oriented in athird selected direction for the flash memory array 600. In theembodiment of FIG. 6D, the first selected direction and the secondselected direction are parallel to one another and orthogonal to thethird selected direction. In this embodiment, the number of bitlines 635serve as address lines.

As will be apparent to one of ordinary skill in the art upon readingthis disclosure, and as will be described in more detail below, writecan still be achieved by hot electron injection and/or, according to theteachings of the present invention, tunneling from the control gate.According to the teachings of the present invention, block erase isaccomplished by driving the control gates with a relatively largepositive voltage and tunneling from the metal on top of the floatinggate to the metal on the bottom of the control gate.

FIG. 7A is an energy band diagram illustrating the band structure atvacuum level with the low tunnel barrier interpoly insulator accordingto the teachings of the present invention. FIG. 7A is useful inillustrating the reduced tunnel barrier off of the floating gate to thecontrol gate and for illustrating the respective capacitances of thestructure according to the teachings of the present invention.

FIG. 7A shows the band structure of the silicon substrate, e.g. channelregion 701, silicon dioxide gate insulator, e.g. gate oxide 703,polysilicon floating gate 705, the low tunnel barrier interpolydielectric 707, between metal plates 709 and 711, and then thepolysilicon control gate 713, according to the teachings of the presentinvention.

The design considerations involved are determined by the dielectricconstant, thickness and tunneling barrier height of the interpolydielectric insulator 707 relative to that of the silicon dioxide gateinsulator, e.g. gate oxide 703. The tunneling probability through theinterpoly dielectric 707 is an exponential function of both the barrierheight and the electric field across this dielectric.

FIG. 7B is an energy band diagram illustrating the band structure duringan erase operation of electrons from the floating gate 705 to thecontrol gate 713 across the low tunnel barrier interpoly insulator 707according to the teachings of the present invention. FIG. 7B issimilarly useful in illustrating the reduced tunnel barrier off of thefloating gate 705 to the control gate 713 and for illustrating therespective capacitances of the structure according to the teachings ofthe present invention.

As shown in FIG. 7B, the electric field is determined by the totalvoltage difference across the structure, the ratio of the capacitances(see FIG. 7A), and the thickness of the interpoly dielectric 707. Thevoltage across the interpoly dielectric 707 will be, ΔV2=V C1/(C1+C2),where V is the total applied voltage. The capacitances, C, of thestructures depends on the dielectric constant, ∈_(r), or thepermittivity of free space, ∈_(o), and the thickness of the insulatinglayers, t, and area, A, such that C=∈_(r)∈_(o) A/t, Farads/cm². Theelectric field across the interpoly dielectric insulator 707, havingcapacitance, C2, will then be E2=ΔV2/t2, where t2 is the thickness ofthis layer.

The tunneling current in erasing charge from the floating gate 705 bytunneling to the control gate 713 will then be as shown in FIG. 7B givenby an equation of the form:J=B exp(−Eo/E)where E is the electric field across the interpoly dielectric insulator707 and Eo depends on the barrier height. Practical values of currentdensities for aluminum oxide which has a current density of 1 A/cm² at afield of about E=1V/20A=5×10⁻ ⁶ V/cm are evidenced in a description byPollack. (See generally, S. R. Pollack and C. E. Morris, “Tunnelingthrough gaseous oxidized films of Al₂O₃,” Trans. AIME, Vol. 233, p. 497,1965). Practical current densities for silicon oxide transistor gateinsulators which has a current density of 1 A/cm² at a field of aboutE=2.3V/23A=1×10+7 V/cm are evidenced in a description by T. P. Ma et al.(See generally, T. P. Ma et al., “Tunneling leakage current in ultrathin(<a4 nm) nitride/oxide stack dielectrics,” IEEE Electron Device Letters,vol. 19, no. 10, pp. 388-390, 1998).

The lower electric field in the aluminum oxide interpoly insulator 707for the same current density reflects the lower tunneling barrier ofless than 2 eV, shown in FIG. 7B, as opposed to the 3.2 eV tunnelingbarrier of silicon oxide 703, also illustrated in FIG. 7B.

FIG. 7C is a graph plotting tunneling currents versus the appliedelectric fields (reciprocal applied electric field shown) for a numberof barrier heights. FIG. 7C illustrates the dependence of the tunnelingcurrents on electric field (reciprocal applied electric field) andbarrier height. The fraction of voltage across the interpoly orintergate insulator, ΔV2, can be increased by making the area of theintergate capacitor, C2, (e.g. intergate insulator 707) smaller than thearea of the transistor gate capacitor, C1 (e.g. gate oxide 703). Thiswould be required with high dielectric constant intergate dielectricinsulators 707 and is easily realized with the vertical floating gatestructures described above in connection with FIGS. 3, and 5A-5E.

Methods of Formation

Several examples are outlined below in order to illustrate how adiversity of such metal oxide tunnel barriers can be formed, accordingto the teachings of the present invention. Processing details andprecise pathways taken which are not expressly set forth below will beobvious to one of ordinary skill in the art upon reading thisdisclosure. Firstly, although not included in the details below, it isimportant also to take into account the following processing factors inconnection with the present invention:

(i) The poly-Si layer is to be formed with emphasis on obtaining asurface that is very smooth and morphologically stable at subsequentdevice processing temperatures which will exceed that used to grow Metaloxide.

(ii) The native SiO_(x) oxide on the poly-Si surface must be removed(e.g., by sputter cleaning in an inert gas plasma in situ) just prior todepositing the metal film. The electrical characteristics of theresultant Poly-Si/Metal/Metal oxide/Metal/Poly-Si structure will bebetter defined and reproducible than that of a Poly-Si/NativeSiO_(x)/Metal/Metal oxide/Poly-Si structure.

(iii) The oxide growth rate and limiting thickness will increase withoxidation temperature and oxygen pressure. The oxidation kinetics of ametal may, in some cases, depend on the crystallographic orientations ofthe very small grains of metal which comprise the metal film (seegenerally, O, Kubaschewski and B. E. Hopkins, “Oxidation of Metals andAlloys”, Butterworth, London, pp. 53-64, 1962). If such effects aresignificant, the metal deposition process can be modified in order toincrease its preferred orientation and subsequent oxide thickness andtunneling uniformity. To this end, use can be made of the fact thatmetal films strongly prefer to grow during their depositions havingtheir lowest free energy planes parallel to the film surface. Thispreference varies with the crystal structure of the metal. For example,fcc metals prefer to form {111 } surface plans. Metal orientationeffects, if present, would be larger when only a limited fraction of themetal will be oxidized and unimportant when all or most of the metal isoxidized.

(iv) Modifications in the structure shown in FIG. 2 may be introduced inorder to compensate for certain properties in some metal/oxide/metallayers. Such changes are reasonable since a wide range of metals, alloysand oxides with quite different physical and chemical properties can beused to form these tunnel junctions.

EXAMPLE 1 Formation of PbO Tunnel Barriers

This oxide barrier has been studied in detail using Pb/PbO/Pbstructures. The oxide itself can be grown very controllably on depositedlead films using either thermal oxidation (see generally, J. M. Eldridgeand J. Matisoo, “Measurement of tunnel current density in aMeal-Oxide-Metal system as a function of oxide thickness,” Proc. 12^(th)Intern. Conf. on Low Temperature Physics, pp. 427-428, 1971; J. M.Eldridge and D. W. Dong, “Growth of thin PbO layers on lead films. I.Experiment,” Surface Science, Vol. 40, pp. 512-530, 1973) or rf sputteretching in an oxygen plasma (see generally, J. H. Greiner, “Oxidation oflead films by rf sputter etching in an oxygen plasma”, J. Appl. Phys.,Vol. 45, No. 1, pp. 32-37, 1974). It will be seen that there are anumber of possible variations on this structure. Starting with a cleanpoly-Si substrate, one processing sequence using thermal oxidationinvolves:

(i) Depositing a clean lead film on the poly-Si floating gate at ˜25 to75 C. in a clean vacuum system having a base pressure of ˜10⁻⁸ Torr orlower. The Pb film will be very thin with a thickness within 1 or 2A ofits target value.

(ii) Lead and other metal films can be deposited by various meansincluding physical sputtering and/or from a Knudsen evaporation cell.The sputtering process also offers the ability to produce smoother filmsby increasing the re-sputtering-to-deposition ratio since re-sputteringpreferentially reduces geometric high points of the film.

(iii) Using a “low temperature oxidation process” to grow an oxide filmof self-limited thickness. In this case, oxygen gas is introduced at thedesired pressure in order to oxidize the lead in situ without anintervening exposure to ambient air. For a fixed oxygen pressure andtemperature, the PbO thickness increases with log(time). Its thicknesscan be controlled via time or other parameters to within 0.10 A, asdetermined via in situ ellipsometric or ex situ measurements ofJosephson tunneling currents. This control is demonstrated by the verylimited statistical scatter of the current PbO thickness data shown inthe insert of FIG. 3 in an article by J. M. Eldridge and J. Matisoo,entitled “Measurement of tunnel current density in a Meal-Oxide-Metalsystem as a function of oxide thickness,” Proc. 12^(th) Intern. Conf. onLow Temperature Physics, pp. 427-428, 1971. This remarkable degree ofcontrol over tunnel current is due to the excellent control over PbOthickness that can be achieved by “low temperature oxidation.” Forexample, increasing the oxidation time from 100 to 1,000 minutes at anoxygen pressure of 750 Torr at 25 C only raises the PbO thickness by 3 A(e.g., from ˜21 to 24 A, see FIG. 1 in J. M. Eldridge and J. Matisoo,“Measurement of tunnel current density in a Meal-Oxide-Metal system as afunction of oxide thickness,” Proc. 12^(th) Intern. Conf. on LowTemperature Physics, pp. 427-428, 1971). Accordingly, controlling theoxidation time to within 1 out of a nominal 100 minute total oxidationtime provides a thickness that is within 0.1 A of 21 A. The PbO has ahighly stoichiometric composition throughout its thickness, as evidencedfrom ellipsometry (e.g., see FIG. 6 in J. M. Eldridge and D. W. Dong,“Growth of thin PbO layers on lead films. I. Experiment,” SurfaceScience, Vol. 40, pp. 512-530, 1973) and the fact that the tunnelbarrier heights are identical for Pb/PbO/Pb structures.

(iv) Re-evacuate the system and deposit the top lead electrode. Thisproduces a tunnel structure having virtually identical tunnel barriersat both Pb/O interfaces.

(v) The temperature used to subsequently deposit the Poly-Si controlgate must be held below the melting temperature (327 C.) of lead. ThePbO itself is stable (up to ˜500 C. or higher) and thus introduces notemperature constraint on subsequent processes. One may optionallyoxidize the lead film to completion, thereby circumventing the lowmelting temperature of metallic lead. In this case, one would form aPoly-Si/PbO/Poly-Si tunnel structure having an altered tunnel barrierfor charge injection. Yet another variation out of several wouldinvolve: oxidizing the lead film to completion; replacing the top leadelectrode with a higher melting metal such as Al; and, then adding thepoly-Si control layer. This junction would have asymmetrical tunnelingbehavior due to the difference in barrier heights between the Pb/PbO andPbO/Al electrodes.

EXAMPLE II Formation of Al₂O₃ Tunnel Barriers

A number of studies have dealt with electron tunneling in Al/A₂O₃/Alstructures where the oxide was grown by “low temperature oxidation” ineither molecular or plasma oxygen (see generally, S. M. Sze, Physics ofSemiconductor Devices, Wiley, N.Y., pp. 553-556, 1981; G. Simmons and A.El-Badry, “Generalized formula for the electric tunnel effect betweensimilar electrodes separated by a thin insulating film,” J. Appl. Phys.,Vol. 34, p. 1793, 1963; S. R. Pollack and C. E. Morris, “Tunnelingthrough gaseous oxidized films of Al₂O₃,” Trans. AIME, Vol. 233, p. 497,1965; Z. Hurych, “Influence of nonuniform thickness of dielectric layerson capacitance and tunnel currents,” Solid-State Electronics, Vol. 9, p.967, 1966; S. P. S. Arya and H. P. Singh, “Conduction properties of thinAl₂O₃ films,” Thin Solid Films, Vol. 91, No. 4, pp. 363-374, May 1982;K.-H. Gundlach and J. Holzl, “Logarithmic conductivity of Al—Al₂O₃—Altunneling junctions produced by plasma- and by thermal-oxidation”,surface Science, Vol. 27, pp. 125-141, 1971). Before sketching out aprocessing sequence for these tunnel barriers, note:

(i) Capacitance and tunnel measurements indicate that the Al₂O₃thickness increases with the log (oxidation time), similar to that foundfor PbO/Pb as well as a great many other oxide/metal systems.

(ii) Tunnel currents are asymmetrical in this system with somewhatlarger currents flowing when electrons are injected from Al/Al₂O₃interface developed during oxide growth. This asymmetry is due to aminor change in composition of the growing oxide: there is a smallconcentration of excess metal in the Al₂O₃, the concentration of whichdiminishes as the oxide is grown thicker. The excess Al⁺³ ions produce aspace charge that lowers the tunnel barrier at the inner interface. Theoxide composition at the outer Al₂O₃/Al contact is much morestoichiometric and thus has a higher tunnel barrier. In situellipsometer measurements on the thermal oxidation of Al films depositedand oxidized in situ support this model (see generally, J. Grimblot andJ. M. Eldridge, “I. Interaction of Al films with O₂ at low pressures”,J. Electro. Chem. Soc., Vol. 129, No. 10, pp. 2366-2368, 1982. J.Grimblot and J. M. Eldridge, “II. Oxidation of Al films”, ibid,2369-2372, 1982). In spite of this minor complication, Al/Al₂O₃/Altunnel barriers can be formed that will produce predictable and highlycontrollable tunnel currents that can be ejected from either electrode.The magnitude of the currents are still primarily dominated by Al₂O₃thickness which can be controlled via the oxidation parametrics.

With this background, we can proceed to outline one process path out ofseveral that can be used to form Al₂O₃ tunnel barriers. Here thealuminum is thermally oxidized although one could use other techniquessuch as plasma oxidation (see generally, S. R. Pollack and C. E. Morris,“Tunneling through gaseous oxidized films of Al₂O₃,” Trans. AIME, Vol.233, p. 497, 1965; K.-H. Gundlach and J. Holzl, “Logarithmicconductivity of Al—Al₂O₃—Al tunneling junctions produced by plasma- andby thermal-oxidation”, Surface Science, Vol. 27, pp. 125-141, 1971) orrf sputtering in an oxygen plasma (see generally, J. H. Greiner,“Oxidation of lead films by rf sputter etching in an oxygen plasma”, J.Appl. Phys., Vol. 45, No. 1, pp. 32-37, 1974). For the sake of brevity,some details noted above will not be repeated. The formation of theAl/Al₂O₃/Al structures will be seen to be simpler than that describedfor the Pb/PbO/Pb junctions owing to the much higher melting point ofaluminum, relative to lead.

(i) Sputter deposit aluminum on poly-Si at a temperature of ˜25 to 150C. Due to thermodynamic forces, the micro-crystallites of the f.c.c.aluminum will have a strong and desirable (111) preferred orientation.

(ii) Oxidize the aluminum in situ in molecular oxygen usingtemperatures, pressure and time to obtain the desired Al₂O₃ thickness.As with PbO, the thickness increases with log (time) and can becontrolled via time at a fixed oxygen pressure and temperature to within0.10 Angstroms, when averaged over a large number of aluminum grainsthat are present under the counter-electrode. One can readily change theAl₂O₃ thickness from ˜15 to 35 A by using appropriate oxidationparametrics (e.g., see FIG. 2 in J. Grimblot and J. M. Eldridge, “II.Oxidation of Al films”, J. Electro. Chem. Soc., Vol. 129, No. 10, pp.2369-2372, 1982). The oxide will be amorphous and remain so untiltemperatures in excess of 400 C. are reached. The initiation ofrecrystallization and grain growth can be suppressed, if desired, viathe addition of small amounts of glass forming elements (e.g., Si)without altering the growth kinetics or barrier heights significantly.

(iii) Re-evacuate the system and deposit a second layer of aluminum.

(iv) Deposit the Poly-Si control gate layer using conventionalprocesses.

EXAMPLE III Formation of Single- and Multi-Layer Transition Metal OxideTunnel Barriers

Single layers of Ta₂O₅, TiO₂, ZrO₂, Nb₂O₅ and similar transition metaloxides can be formed by “low temperature oxidation” of numerousTransition Metal (e.g., TM oxides) films in molecular and plasma oxygenand also by rf sputtering in an oxygen plasma. The thermal oxidationkinetics of these metals have been studied for decades with numerousdescriptions and references to be found in the book by Kubaschewski andHopkins (0. Kubaschewski and B. E. Hopkins, “Oxidation of Metals andAlloys”, Butterworth, London, pp. 53-64, 1962). In essence, such metalsoxidize via logarithmic kinetics to reach thicknesses of a few toseveral tens of angstroms in the range of 100 to 300 C. Excellent oxidebarriers for Josephson tunnel devices can be formed by rf sputteretching these metals in an oxygen plasma (see generally, J. M. Greiner,“Josephson tunneling barriers by rf sputter etching in an oxygenplasma,” J. Appl. Phys., Vol. 42, No. 12, pp. 5151-5155, 1971; O.Michikami et al., “Method of fabrication of Josephson tunnel junctions,”U.S. Pat. No. 4,412,902, Nov. 1, 1983). Such “low temperature oxidation”approaches differ considerably from MOCVD processes used to producethese TM oxides. MOCVD films require high temperature oxidationtreatments to remove carbon impurities, improve oxide stoichiometry andproduce recrystallization. Such high temperature treatments also causeunwanted interactions between the oxide and the underlying silicon andthus have necessitated the introduction of interfacial barrier layers.See, for example, H. F. Luan et al., “High quality Ta₂O₅ gatedielectrics with T_(ox,eq)<10 angstroms,” IEDM Tech. Digest, pp.141-144, 1999.

A new approach was described in a copending application by J. M.Eldridge, entitled “Thin Dielectric Films for DRAM Storage Capacitors,”patent application Ser. No. 09/651,380 filed Aug. 29, 2000 that utilizes“low temperature oxidation” to form duplex layers of TM oxides. UnlikeMOCVD films, the oxides are very pure and stoichiometric as formed. Theydo require at least a brief high temperature (est. 700 to 800 C but maybe lower) treatment to transform their microstructures from amorphous tocrystalline and thus increase their dielectric constants to the desiredvalues (>20 or so). Unlike MOCVD oxides, this treatment can be carriedout in an inert gas atmosphere, thus lessening the possibility ofinadvertently oxidizing the poly-Si floating gate. While this earlierdisclosure was directed at developing methods and procedures forproducing high dielectric constant films for storage cells for DRAMs,the same teachings can be applied to producing thinner metal oxidetunnel films for the flash memory devices described in this disclosure.The dielectric constants of these TM oxides are substantially greater(>25 to 30 or more) than those of PbO and Al₂O₃. Duplex layers of thesehigh dielectric constant oxide films are easily fabricated with simpletools and also provide improvement in device yields and reliability.Each oxide layer will contain some level of defects but the probabilitythat such defects will overlap is exceedingly small. Effects of suchduplex layers were first reported by one J. M. Eldridge of the presentauthors and are well known to practitioners of the art. It is worthmentioning that highly reproducible TM oxide tunnel barriers can begrown by rf sputtering in an oxygen ambient, as referenced above (seegenerally, J. M. Greiner, “Josephson tunneling barriers by rf sputteretching in an oxygen plasma,” J. Appl. Phys., Vol. 42, No. 12, pp.5151-5155, 1971; O. Michikami et al., “Method of fabrication ofJosephson tunnel junctions,” U.S. Pat. No. 4,412,902, Nov. 1, 1983).Control over oxide thickness and other properties in these studies wereall the more remarkable in view of the fact that the oxides weretypically grown on thick (e.g., 5,000 A) metals such as Nb and Ta. Insuch metal-oxide systems, a range of layers and suboxides can also form,each having their own properties. In the present disclosure, controlover the properties of the various TM oxides will be even better sincewe employ very limited (perhaps 10 to 100 A or so) thicknesses of metaland thereby preclude the formation of significant quantities ofunwanted, less controllable sub-oxide films. Thermodynamic forces willdrive the oxide compositions to their most stable, fully oxidized state,e.g., Nb₂O₅, Ta₂O₅, etc. As noted above, it will still be necessary tocrystallize these duplex oxide layers. Such treatments can be done byRTP and will be shorter than those used on MOCVD and sputter-depositedoxides since the stoichiometry and purity of the “low temperatureoxides” need not be adjusted at high temperature.

Fairly detailed descriptions for producing thicker duplex layers of TMoxides have been given in the copending application by J. M. Eldridge,entitled “Thin Dielectric Films for DRAM Storage Capacitors,” patentapplication Ser. No. 09/651,380 filed Aug. 29, 2000, so there is no needto repeat them here. Although perhaps obvious to those skilled in theart, one can sketch out a few useful fabrication guides:

(i) Thinner TM layers will be used in this invention relative to thoseused to form DRAMs. Unlike DRAMs where leakage must be eliminated, theduplex oxides used here must be thin enough to carry very controlledlevels of current flow when subjected to reasonable applied fields andtimes.

(ii) The TM and their oxides are highly refractory and etchable (e.g.,by RIE). Hence they are quite compatible with poly-Si control gateprocesses and other subsequent steps.

(iii) TM silicide formation will not occur during the oxidation step. Itcould take place at a significant rate at the temperatures used todeposit the poly-Si control gate. If so, several solutions can beapplied including:

-   -   (i) Insert certain metals at the TM/poly-Si boundaries that will        prevent inter-diffusion of the TM and the poly-Si.    -   (ii) Completely oxide the TMs. The electrical characteristics of        the resulting poly-Si/TM oxide 1/TM oxide 2/poly-Si structure        will be different in the absence of having TM at the oxide/metal        interfaces.

EXAMPLE IV Formation of Alternate Metal Compound Tunnel Barriers

Although no applications may be immediately obvious, it is conceivablethat one might want to form a stack of oxide films having quitedifferent properties, for example, a stack comprised of a highdielectric constant (k) oxide/a low k oxide/a high k oxide. “Lowtemperature oxidation” can be used to form numerous variations of suchstructures. While most of this disclosure deals with the formation anduse of stacks of oxide dielectrics, it is also possible to use “lowtemperature oxidation” to form other thin film dielectrics such asnitrides, oxynitrides, etc. that could provide additional functions suchas being altered by monochromatic light, etc. These will not bediscussed further here.

EXAMPLE V Formation of Perovskite Oxide Tunnel Barriers

Some results have been obtained which demonstrate that at least alimited range of high temperature, super-conducting oxide films can bemade by thermally oxidizing Y—Ba—Cu alloy films (see generally, Hase etal., “Method of manufacturing an oxide superconducting film,” U.S. Pat.No. 5,350,738, Sep. 27, 1994). The present inventors have also disclosedhow to employ “low temperature oxidation” and short thermal treatmentsin an inert ambient at 700 C. in order to form a range of perovskiteoxide films from parent alloy films (see generally, J. M. Eldridge, “LowCost Processes for Producing High Quality Perovskite Dielectric Films,”application Ser. No. 09/945,137). The dielectric constants ofcrystallized, perovskite oxides can be very large, with values in the100 to 1000 or more range. The basic process is more complicated thanthat needed to oxidize layered films of transition metals. (See ExampleIII.) The TM layers would typically be pure metals although they couldbe alloyed. The TMs are similar metallurgically as are their oxides. Incontrast, the parent alloy films that can be converted to a perovskiteoxide are typically comprised of metals having widely different chemicalreactivities with oxygen and other common gasses. In the Y—Ba—Cu systemreferenced above, Y and Ba are among the most reactive of metals whilethe reactivity of Cu approaches (albeit distantly) those of other noblemetals. If the alloy is to be completely oxidized, then thin filmbarriers such as Pd, Pt, etc. or their conductive oxides must be addedbetween the Si and the parent metal film to serve as: electrical contactlayers; diffusion barriers; and, oxidation stops. In such a case, theSchottky barrier heights of various TM oxides and perovskite oxides incontact with various metals will help in the design of the tunneldevice. In the more likely event that the perovskite parent alloy filmwill be only partially converted to oxide and then covered with a secondlayer of the parent alloy (recall the structure of FIG. 2), then thebarrier heights will represent that developed during oxide growth at theparent perovskite alloy/perovskite oxide interface. Obviously, suchbarrier heights cannot be predicted ab initio for such a wide class ofmaterials but will have to be developed as the need arises. Thisinformation will have to be developed on a system-by-system basis.

Methods of Operation

Write Operation

Write can be achieved by the normal channel hot electron injection andgate current through the silicon oxide to the floating gate. This isdone by selecting a particular column by applying a high control gatevoltage and applying relatively large drain voltage as is done withconventional ETOX flash memory devices. However, according to theteachings of the present invention, write can also be accomplished byapplying a positive voltage to the substrate or well select line and alarge negative voltage to the control gates, electrons will tunnel fromthe control gate to the floating gate. The low tunnel barrier willprovide an easy write operation and the selection of the substrate orwell bias will provide selectivity and address only one device.

Erase Operation

According to the teachings of the present invention, erase is achievedby providing a negative voltage to the substrate or well address lineand a large positive voltage to the control gate. This causes electronsto tunnel off of the floating gate on to the control gate. A whole rowcan be erased by addressing all the column lines along that row and ablock can be erased by addressing multiple row back gate orsubstrate/well address lines.

Read Operation

Read is accomplished as in conventional ETOX flash memory devices. Acolumn line is addressed by applying a positive control gate voltage andsensing the current along the data bit or drain row address line.

System Level

FIG. 8 illustrates a block diagram of an embodiment of an electronicsystem 801 according to the teachings of the present invention. In theembodiment shown in FIG. 8, the system 801 includes a memory device 800which has an array of memory cells 802, address decoder 804, row accesscircuitry 806, column access circuitry 808, control circuitry 810, andinput/output circuit 812. Also, as shown in FIG. 8, the circuit 801includes a processor 814, or memory controller for memory accessing. Thememory device 800 receives control signals from the processor 814, suchas WE*, RAS* and CAS* signals over wiring or metallization lines. Thememory device 800 is used to store data which is accessed via I/O lines.It will be appreciated by those skilled in the art that additionalcircuitry and control signals can be provided, and that the memorydevice 800 has been simplified to help focus on the invention. At leastone of the memory cells 802 has a memory cell formed according to theembodiments of the present invention. That is, at least one memory cellincludes a low tunnel barrier interpoly insulator according to theteachings of the present invention.

It will be understood that the embodiment shown in FIG. 8 illustrates anembodiment for electronic system circuitry in which the novel memorycells of the present invention are used. The illustration of system 801,as shown in FIG. 8, is intended to provide a general understanding ofone application for the structure and circuitry of the presentinvention, and is not intended to serve as a complete description of allthe elements and features of an electronic system using the novel memorycell structures. Further, the invention is equally applicable to anysize and type of memory device 801 using the novel memory cells of thepresent invention and is not intended to be limited to that describedabove. As one of ordinary skill in the art will understand, such anelectronic system can be fabricated in single-package processing units,or even on a single semiconductor chip, in order to reduce thecommunication time between the processor and the memory device.

Applications containing the novel memory cell of the present inventionas described in this disclosure include electronic systems for use inmemory modules, device drivers, power modules, communication modems,processor modules, and application-specific modules, and may includemultilayer, multichip modules. Such circuitry can further be asubcomponent of a variety of electronic systems, such as a clock, atelevision, a cell phone, a personal computer, an automobile, anindustrial control system, an aircraft, and others.

CONCLUSION

The above structures and fabrication methods have been described, by wayof example, and not by way of limitation, with respect to flash memorywith low tunnel barrier interpoly insulators ultra thin bodytransistors.

It has been shown that the low tunnel barrier interpoly insulators ofthe present invention avoid the large barriers to electron tunneling orhot electron injection presented by the silicon oxide-silicon interface,3.2 eV, which result in slow write and erase speeds even at very highelectric fields. The present invention also avoids the combination ofvery high electric fields and damage by hot electron collisions in thewhich oxide result in a number of operational problems like soft eraseerror, reliability problems of premature oxide breakdown and a limitednumber of cycles of write and erase. Further, the low tunnel barrierinterploy dielectric insulator erase approach, of the present inventionremedies the above mentioned problems of having a rough top surface onthe polysilicon floating gate which results in, poor quality interpolyoxides, sharp points, localized high electric fields, prematurebreakdown and reliability problems.

The above mentioned problems with flash memories and other problems areaddressed by the present invention and will be understood by reading andstudying the specification. Systems and methods are provided for flashmemories with metal oxide and/or low tunnel barrier interpolyinsulators.

In one embodiment of the present invention, the non-volatile memoryincludes a first source/drain region and a second source/drain regionseparated by a channel region in a substrate. A floating gate opposingthe channel region and is separated therefrom by a gate oxide. A controlgate opposes the floating gate. The control gate is separated from thefloating gate by a low tunnel barrier intergate insulator. The lowtunnel barrier intergate insulator includes a metal oxide insulatorselected from the group consisting of PbO, Al₂O₃, Ta₂O₅, TiO₂, ZrO₂, andNb₂O₅. The floating gate includes a polysilicon floating gate having ametal layer formed thereon in contact with the low tunnel barrierintergate insulator. And, the control gate includes a polysiliconcontrol gate having a metal layer formed thereon in contact with the lowtunnel barrier intergate insulator.

These and other embodiments, aspects, advantages, and features of thepresent invention will be set forth in part in the description, and inpart will become apparent to those skilled in the art by reference tothe following description of the invention and referenced drawings or bypractice of the invention. The aspects, advantages, and features of theinvention are realized and attained by means of the instrumentalities,procedures, and combinations particularly pointed out in the appendedclaims.

1. A method for forming an array of flash memory cells, comprising:forming a number of pillars extending outwardly from a substrate,wherein each pillar includes a first source/drain region, a body region,and a second source/drain region; forming a number of floating gatesopposing the body regions in the number of pillars and separatedtherefrom by a gate oxide; forming a number of control gates opposingthe floating gates; forming a number of buried sourcelines disposedbelow the number of pillars and coupled to the first source/drainregions along a first selected direction in the array of memory cells;forming a number of control gate lines formed integrally with the numberof control gates along a second selected direction in the array of flashmemory cells, wherein the number of control gates lines are separatedfrom the floating gates by a low tunnel barrier intergate insulator; andforming a number of bitlines coupled to the second source/drain regionsalong a third selected direction in the array of flash cells.
 2. Themethod of claim 1, wherein forming the low tunnel barrier intergateinsulator includes forming a metal oxide insulator selected from thegroup consisting of PbO, Al₂O₃, TiO₂, ZrO₂, and Nb₂O₅.
 3. The method ofclaim 1, wherein forming each floating gate includes forming apolysilicon floating gate having a metal layer formed thereon in contactwith the low tunnel barrier intergate insulator.
 4. The method of claim1, wherein forming each control gate includes forming a polysiliconcontrol gate having a metal layer formed thereon in contact with the lowtunnel barrier intergate insulator.
 5. The method of claim 1, whereinforming each floating gate includes forming a vertical floating gate ina trench below a top surface of each pillar such that each trench housesa pair of floating gates opposing the body regions in adjacent pillarson opposing sides of the trench.
 6. The method of claim 5, whereinforming the plurality of control gate lines includes forming eachcontrol gate line in the trench below the top surface of the pillar andbetween the pair of floating gates, wherein each pair of floating gatesshares a single control gate line, and wherein each floating gateincludes a vertically oriented floating gate having a vertical length ofless than 100 nanometers.
 7. The method of claim 5, wherein forming theplurality of control gate lines includes forming a pair of control gatelines in each trench below the top surface of the pillar and between thepair of floating gates such that each control gate line addresses afloating gate on opposing sides of the trench respectively, and whereinthe pair of control gate lines are separated by an insulator layer. 8.The method of claim 5, wherein forming the plurality of control gatelines includes forming the control gate lines such that the control gatelines are disposed vertically above the floating gates such that eachpair of floating gates shares a single control gate line.
 9. The methodof claim 5, wherein forming the plurality of control gate lines includesforming the control gate lines such that the control gate lines aredisposed vertically above the floating gates, and forming the pluralityof control lines such that each one of the pair of floating gates isaddressed by an independent one of the plurality of control lines. 10.The method of claim 1, wherein forming each floating gate includesforming a horizontally oriented floating gate in a trench below a topsurface of each pillar such that each trench houses a floating gateopposing the body regions in adjacent pillars on opposite sides of thetrench, and wherein each horizontally oriented floating gate has avertical length of less than 100 nanometers opposing the body region ofthe pillars.
 11. The method of claim 10, wherein the forming theplurality of control gate lines includes forming the control gate linessuch that the control gate lines are disposed vertically above thefloating gates.
 12. A method for forming an array of non-volatile memorycells, comprising: forming a number of pillars extending outwardly froma substrate, wherein each pillar includes a first source/drain region, abody region, and a second source/drain region; forming a number offloating gates opposing the body regions in the number of pillars andseparated therefrom by a gate oxide; forming a number of control gatesopposing the floating gates; forming a number of buried sourcelinesdisposed below the number of pillars and coupled to the firstsource/drain regions along a first selected direction in the array ofmemory cells; forming a low tunnel barrier, Ta₂O₅ intergate insulator;forming a number of control gate lines formed integrally with the numberof control gates along a second selected direction in the array of flashmemory cells, wherein the number of control gates lines are separatedfrom the floating gates by the low tunnel barrier intergate insulator;and forming a number of bitlines coupled to the second source/drainregions along a third selected direction in the array of flash cells.13. The method of claim 12, wherein forming each floating gate includesforming a polysilicon floating gate having a metal layer formed thereonin contact with the low tunnel barrier intergate insulator.
 14. Themethod of claim 12, wherein forming each control gate includes forming apolysilicon control gate having a metal layer formed thereon in contactwith the low tunnel barrier intergate insulator.
 15. The method of claim12, wherein forming each floating gate includes forming a verticalfloating gate in a trench below a top surface of each pillar such thateach trench houses a pair of floating gates opposing the body regions inadjacent pillars on opposing sides of the trench.
 16. The method ofclaim 15, wherein forming the plurality of control gate lines includesforming each control gate line in the trench below the top surface ofthe pillar and between the pair of floating gates, wherein each pair offloating gates shares a single control gate line, and wherein eachfloating gate includes a vertically oriented floating gate having avertical length of less than 100 nanometers.
 17. The method of claim 15,wherein forming the plurality of control gate lines includes forming apair of control gate lines in each trench below the top surface of thepillar and between the pair of floating gates such that each controlgate line addresses a floating gate on opposing sides of the trenchrespectively, and wherein the pair of control gate lines are separatedby an insulator layer.
 18. The method of claim 15, wherein forming theplurality of control gate lines includes forming the control gate linessuch that the control gate lines are disposed vertically above thefloating gates such that each pair of floating gates shares a singlecontrol gate line.
 19. The method of claim 15, wherein forming theplurality of control gate lines includes forming the control gate linessuch that the control gate lines are disposed vertically above thefloating gates, and forming the plurality of control lines such thateach one of the pair of floating gates is addressed by an independentone of the plurality of control lines.
 20. The method of claim 12,wherein forming each floating gate includes forming a horizontallyoriented floating gate in a trench below a top surface of each pillarsuch that each trench houses a floating gate opposing the body regionsin adjacent pillars on opposite sides of the trench, and wherein eachhorizontally oriented floating gate has a vertical length of less than100 nanometers opposing the body region of the pillars.
 21. The methodof claim 20, wherein the forming the plurality of control gate linesincludes forming the control gate lines such that the control gate linesare disposed vertically above the floating gates.
 22. A method forforming an array of flash memory cells, comprising: forming a number ofpillars extending outwardly from a substrate, wherein each pillarincludes a first source/drain region, a body region, and a secondsource/drain region; forming a number of floating gates opposing thebody regions in the number of pillars and separated therefrom by a gateoxide, wherein forming each floating gate includes forming a polysiliconfloating gate having a metal layer formed thereon in contact with thelow tunnel barrier intergate insulator; forming a number of controlgates opposing the floating gates, wherein forming each control gateincludes forming a polysilicon control gate having a metal layer formedthereon in contact with the low tunnel barrier intergate insulator;forming a number of buried sourcelines disposed below the number ofpillars and coupled to the first source/drain regions along a firstselected direction in the array of memory cells; forming a number ofcontrol gate lines formed integrally with the number of control gatesalong a second selected direction in the array of flash memory cells,wherein the number of control gates lines are separated from thefloating gates by a low tunnel barrier intergate insulator; and forminga number of bitlines coupled to the second source/drain regions along athird selected direction in the array of flash cells.
 23. The method ofclaim 22, wherein forming the low tunnel barrier intergate insulatorincludes forming a metal oxide insulator selected from the groupconsisting of PbO, Al₂O₃, Ta₂O₅, TiO₂, ZrO₂, and Nb₂O₅.
 24. The methodof claim 23, wherein forming each floating gate includes forming avertical floating gate in a trench below a top surface of each pillarsuch that each trench houses a pair of floating gates opposing the bodyregions in adjacent pillars on opposing sides of the trench.